Logic simulator is an essential electronic design automation (EDA) tool to facilitate the design and debug of very large scale integrated (VLSI) circuit. Examples of these VLSI designs include microprocessors for personal computers and workstations, micro-controllers for embedded systems, and internetworking routers and switches, etc. The VLSI circuit designers use logic simulators to simulate and verify the functional behavior and timing characteristics of their circuit designs on their engineering workstations before committing such designs to fabrication. The benefits of the logic simulators are to reduce new product development time and costs, and to improve engineer productivity and product quality.
Referring to FIG. 1, the operations of a logic simulator is depicted. Specifically, a user""s inputs to a logic simulator are one or more text files, which describe the specification of his circuit. These design files are usually coded in a hardware description language (HDL). In addition, the user also provides an input stimulus file to the simulator. This file may consist of input vectors to be applied to the circuit at specified time intervals, and/or some behavioral HDL code that describes how various signals (i.e., clocks and global reset signals) in the circuits are to change states during the simulation.
The logic simulator compiles the design files and stimulus file supplied by the user into a database. It may flag any errors it detects in the design files or stimulus file. These errors may include syntax errors, undefined library cells, signals with no driver and/or receivers, and bus contentions, etc. After the input files are successfully compiled, the logic simulator applies input stimulus to the circuit and performs simulation of the circuit for the duration of time as specified by the user. During simulation, the simulator also keeps track of the changes of states of any user-selected signals in the design. At the completion of the simulation, the simulator will bring up a graphical waveform window or a tabular state-listing window to show the user the selected signal states for the entire simulation run.
There are two types of logic simulators being widely used namely, event-driven logic simulator and cycle-based logic simulator. The event-driven logic simulators are the traditional simulators, which model both the functional and timing behaviors of user circuits. They can be applied for any type of digital designs. The cycle-based simulator, on the other hand, models only the functional behaviors of user designs. Thus, a cycle-based simulator runs faster (up to 10 time or more) than an event-driven simulator, but it does not provide timing verification of user designs and is suitable only for synchronous designs (synchronous designs are those that one or more master clocks controlling all activities in the designs)
In the 1980s to early 1990s, most EDA vendors offered event-driven logic simulators running on either UNIX-based workstations or Windows-based personal computers. However, as VLSI designs get larger and more complex, the time to perform simulation on those general-purpose workstations and personal computers grew exponentially. To reduce the design verification time, many EDA vendors are offering cycle-based simulators to allow users, at their own elections, to trade-off accuracy with speed. Users who use cycle-based simulators must also use a separate tool (e.g., a static timing analyzer) to verify the correctness of the timing characters of their designs.
Besides offering cycle-based simulators, some EDA vendors have introduced hardware-accelerators or hardware emulators to speed up the simulation of large designs. Specifically, a hardware accelerator hardwires the logic simulation algorithm into hardware, so that it can speedup the simulation of any given design by 10 to 100 times. A hardware emulator, on the other hand, programs a group of field-programmable gate array (FPGA) chips to emulate the logic functions of a given design, and it xe2x80x9csimulatesxe2x80x9d the designs in real hardware speed. A hardware emulator can speedup simulation by a 1000 times or more. The drawback of the hardware accelerators and hardware emulators are that they are very expansive and designers can use them only on a time-sharing basis. Thus, they are mostly used as regression testing tools and not a debug tool. Furthermore, since they do not accurately model timing characteristic of user designs, the users still need to use other tools, like a static timing analyzer, to verify the timing behavior of their circuits separately.
With the recent introduction of multiprocessor workstations (UNIX-based and Windows(trademark)-based), some EDA vendors have realized that they can accelerate their tools performance by porting their applications onto such workstations. By using multiple microprocessors (CPUs) concurrently on these workstations, the performance of their tools can rival that of hardware accelerators and emulators, while still provides all the benefits of a traditional logic simulator. Furthermore, the multiprocessor workstations cost much less (i.e., ten to hundred times less) than that of hardware accelerators and emulators, and can be used for other engineering services in addition to logic simulation (e.g., act as file servers or electronic mail servers). Thus, use of multiprocessor workstations in VLSI design houses seems to be the future trend in the industry.
EDA tools that employ multiple CPUs on a single workstation to accelerate their performance are said to be multithreaded. Specifically, a thread is a process flow in a program that runs on a CPU. If a program can have multiple threads executing on multiple CPUs concurrently, then its is a multithreaded applications. Most EDA applications available today are single-threaded, which means that those applications performance on a multiprocessor system is still the same as that running on a single system.
Most VLSI designers use a hardware description language (HDL) to write their designs. The most commonly used hardware description languages are VHDL (VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit) and Verilog. They are standardized by the IEEE (Institute of Electrical and Electronic Engineering) society, and are widely supported by the electronics and semiconductor industries around the world. Most commercial logic simulators support either VHDL or Verilog language. A few EDA vendors provide a simulation backplane to interconnect a VHDL and a Verilog simulator, so that a user can simulate his VLSI design coded in both VHDL and Verilog. These products are not very popular as they are expensive (i.e., users need to purchase two separate simulators and the backplane) and inefficient in their performance.
Referring to Table 1, it lists the major commercial HDL logic simulators, their features and the HDL languages they supported. There are currently three EDA vendors that sell multithreaded logic simulators. Synopsys Incorporated sells a multithreaded event-driven logic simulator on UNIX platforms; QuickTurn Design Systems and Avanti Corporation offer multithreaded cycle-based logic simulators on UNIX platforms. It is noted, however, none of these vendors offers any multithreaded logic simulators that support the multiprocessor Linux and Windows(trademark) platforms. In addition, It should be further noted there is no commercial logic simulator that supports both the VHDL and Verilog languages, and is also multithreaded.
There is therefore an apparent need for a general-purpose multithreaded logic simulator that supports both the VHDL and Verilog languages in a single program to perform both a event-driven and a cycle-based logic simulation on a multiprocessor platform chosen by a user. There is a further need that such general-purpose multithreaded logic simulator can support both the local and remote users through its network resources.
Accordingly, one object of the invention is to provide for a new multithreaded logic simulator that uses unique algorithms to achieve excellent performance on multi-CPU platforms (e.g., UNIX, Linux, and Windows(trademark)), and yet supports both the VHDL and Verilog languages in a single program such that the simulator can be used in any HDL design environments. The users do not need to maintain expensive workstations or separate VHDL and Verilog simulators to reduce product development costs.
Another object of the invention is to provide for a logic simulator that allows users to learn only one single simulator and yet be able to code their HDL designs in either VHDL and/or Verilog, which can be subsequently verified on any of the UNIX, Linux, or Windows(trademark) platforms, to improve users"" engineering productivity and shorten product development time and costs.
One more object of the invention is to provide for a logic simulator that allows users to easily import any design source files (e.g., intellectual property core logic design) from any third party design house and simulate such design source files with their own design regardless whether the third party design files are coded in the users"" own HDL languages or not to further improve engineering productivity and to shorten product development time and costs.
Still one object of the invention is to provide for a unique new network-based simulation method to facilitate VLSI designers to make full use of their network resources to perform logic simulation. Specifically, the VLSI designers can treat all their networked (single- or multi-processor) machines as one giant computer, and to perform compilation and simulation of their designs on their local desktop computers or any other computers on the network. This method not only improves users"" engineering productivity, but also improves the return of investment of users"" hardware and software resources. This new method is not described or implemented in any prior arts.
In addition to all the above, one more object of the invention is to provide for a logic simulator that provides a simulation job scheduling method which allows users to schedule compilation and simulation of their designs on any remote or local (single- or multi-processor) machines, at their specified time(s). This feature allows large design groups to schedule and balance the workload of their network machines, as well as to define periodic regression testing of their VLSI designs. The job-scheduling feature is not described or implemented in any prior arts. As described above, this feature provides further benefits to improve users"" engineering productivity as well as to users"" return of hardware and software investments.
Finally, another object of the invention is to provide for a logic simulator whose multithreaded capability allows users to reduce drastically their simulation time on multiprocessor platforms to reduce development costs and time, and to improve engineering productivity and product quality.
This invention describes a novel concurrent, multithreaded algorithm to accelerate the execution of logic simulation of HDL (VHDL and/or Verilog) designs on any general-purpose multi-processor computer systems including, but without limitation to, UNIX, Linux, and Windows(trademark) platforms. The algorithm enables the logic simulator provided by the invention to achieve a scalable performance (i.e., from linear to super-linear) according to the number of CPUs on the selected platform.
This invention describes further a novel HDL logic simulator that supports both VHDL and Verilog HDL design languages in a single program, and is multithreaded on any platforms. These features allow VLSI chip and/or system designers to mix-and-match their HDL designs (Verilog and/or VHDL) and run simulation on any hardware resources they have available.
One aspect of the invention is to provide for a novel HDL simulator that provides seamless access of network resources for HDL design compilation and simulation. Specifically, by installing a server program which runs on any of the remote workstations including, but without limitation to, UNIX, Linux, or Windows(trademark), users can access design files on any of such machines directly from their respective computers, via a user-interface (xe2x80x9cUIxe2x80x9d or xe2x80x9cUIsxe2x80x9d) program(s). Furthermore, the users can instruct (via their local UIs) remote servers to compile and/or simulate HDL designs on the server hosts. The remote compilation and/or simulation results are automatically transferred back to the user"" local hosts and are displayed on their UIs.
Another aspect of the invention is to provide for a novel HDL simulator to provide simulation job scheduling on local and/or remote platforms including, but not limited to, UNIX, Linux, and Windows(trademark). This features allow VLSI designers to balance the work loads on their network resources by scheduling simulation runs at off-peak hours, as well as to automate the regular regression testing of their designs.